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<div class="header">
  <div class="summary">
<a href="#pub-attribs">Data Fields</a>  </div>
  <div class="headertitle"><div class="title">CPACR_Type Struct Reference<div class="ingroups"><a class="el" href="group__CMSIS__core__register.html">Core Register Access</a> &raquo; <a class="el" href="group__CMSIS__CPACR.html">Coprocessor Access Control Register (CPACR)</a></div></div></div>
</div><!--header-->
<div class="contents">

<p>Bit field declaration for CPACR layout.  
 <a href="unionCPACR__Type.html#details">More...</a></p>

<p><code>#include &lt;core_ca.h&gt;</code></p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="pub-attribs" name="pub-attribs"></a>
Data Fields</h2></td></tr>
<tr class="memitem:ac3126dff3427fa6f4ab48524d473aa12"><td class="memItemLeft" >struct {</td></tr>
<tr class="memitem:a5fc0fc99aac224f0b602b067dab8d07e"><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="unionCPACR__Type.html#a1a29bc40d708ac1a43153b11f60b8195">CP0</a>:2</td></tr>
<tr class="memdesc:a5fc0fc99aac224f0b602b067dab8d07e"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 0..1 Access rights for coprocessor 0  <a href="unionCPACR__Type.html#a1a29bc40d708ac1a43153b11f60b8195">More...</a><br /></td></tr>
<tr class="separator:a5fc0fc99aac224f0b602b067dab8d07e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1188eed16602e13bfa581efd582cd25f"><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="unionCPACR__Type.html#acb2055cdbdf2a6c9b8279dc6f7cbc624">CP1</a>:2</td></tr>
<tr class="memdesc:a1188eed16602e13bfa581efd582cd25f"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 2..3 Access rights for coprocessor 1  <a href="unionCPACR__Type.html#acb2055cdbdf2a6c9b8279dc6f7cbc624">More...</a><br /></td></tr>
<tr class="separator:a1188eed16602e13bfa581efd582cd25f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2b8936ec0e3d5618af338a51ba703bdf"><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="unionCPACR__Type.html#a2553fcdfd94ffc09407db9da9db9d586">CP2</a>:2</td></tr>
<tr class="memdesc:a2b8936ec0e3d5618af338a51ba703bdf"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 4..5 Access rights for coprocessor 2  <a href="unionCPACR__Type.html#a2553fcdfd94ffc09407db9da9db9d586">More...</a><br /></td></tr>
<tr class="separator:a2b8936ec0e3d5618af338a51ba703bdf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a85a47574930ac1d3bf6759a47462fc34"><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="unionCPACR__Type.html#af245b8dabfea0bf7dc06f5d4de7bfa79">CP3</a>:2</td></tr>
<tr class="memdesc:a85a47574930ac1d3bf6759a47462fc34"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 6..7 Access rights for coprocessor 3  <a href="unionCPACR__Type.html#af245b8dabfea0bf7dc06f5d4de7bfa79">More...</a><br /></td></tr>
<tr class="separator:a85a47574930ac1d3bf6759a47462fc34"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae7ed18f044a639b62e7a18f701b03db7"><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="unionCPACR__Type.html#a6424b7a81a440217aab8e51e4b623adb">CP4</a>:2</td></tr>
<tr class="memdesc:ae7ed18f044a639b62e7a18f701b03db7"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 8..9 Access rights for coprocessor 4  <a href="unionCPACR__Type.html#a6424b7a81a440217aab8e51e4b623adb">More...</a><br /></td></tr>
<tr class="separator:ae7ed18f044a639b62e7a18f701b03db7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3920ba5d4caebac449dd73cd89344501"><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="unionCPACR__Type.html#ad5c0b15cd6a01a6f1db398e020809573">CP5</a>:2</td></tr>
<tr class="memdesc:a3920ba5d4caebac449dd73cd89344501"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit:10..11 Access rights for coprocessor 5  <a href="unionCPACR__Type.html#ad5c0b15cd6a01a6f1db398e020809573">More...</a><br /></td></tr>
<tr class="separator:a3920ba5d4caebac449dd73cd89344501"><td class="memSeparator" colspan="2">&#160;</td></tr>
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<tr class="memdesc:a0eca61032fc0279645454dcb141ea85e"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit:12..13 Access rights for coprocessor 6  <a href="unionCPACR__Type.html#ad898cab7c89a07b80068d141ced869e3">More...</a><br /></td></tr>
<tr class="separator:a0eca61032fc0279645454dcb141ea85e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad730fda88046a10892bf869da17eed6c"><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="unionCPACR__Type.html#a12002991719fb1af7a5db9a73deb323d">CP7</a>:2</td></tr>
<tr class="memdesc:ad730fda88046a10892bf869da17eed6c"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit:14..15 Access rights for coprocessor 7  <a href="unionCPACR__Type.html#a12002991719fb1af7a5db9a73deb323d">More...</a><br /></td></tr>
<tr class="separator:ad730fda88046a10892bf869da17eed6c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2a0b25d17051694d69996966de4a6450"><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="unionCPACR__Type.html#a5a6f694264518a813bdbc202ff47664f">CP8</a>:2</td></tr>
<tr class="memdesc:a2a0b25d17051694d69996966de4a6450"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit:16..17 Access rights for coprocessor 8  <a href="unionCPACR__Type.html#a5a6f694264518a813bdbc202ff47664f">More...</a><br /></td></tr>
<tr class="separator:a2a0b25d17051694d69996966de4a6450"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a911420120954a07b65a4bfdcfd5810ea"><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="unionCPACR__Type.html#a4de69636eb450fcc3f5f3e4a19a869f5">CP9</a>:2</td></tr>
<tr class="memdesc:a911420120954a07b65a4bfdcfd5810ea"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit:18..19 Access rights for coprocessor 9  <a href="unionCPACR__Type.html#a4de69636eb450fcc3f5f3e4a19a869f5">More...</a><br /></td></tr>
<tr class="separator:a911420120954a07b65a4bfdcfd5810ea"><td class="memSeparator" colspan="2">&#160;</td></tr>
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<tr class="memdesc:afab63379024b243f644562ccc042a2bb"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit:20..21 Access rights for coprocessor 10  <a href="unionCPACR__Type.html#a0275dc6b0eb9f906ebc5c6431b03dc4e">More...</a><br /></td></tr>
<tr class="separator:afab63379024b243f644562ccc042a2bb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a19f2a2270bc7aa8c4177d6e384197ea2"><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="unionCPACR__Type.html#ac54b8897f9358f37e0046b010c334e87">CP11</a>:2</td></tr>
<tr class="memdesc:a19f2a2270bc7aa8c4177d6e384197ea2"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit:22..23 Access rights for coprocessor 11  <a href="unionCPACR__Type.html#ac54b8897f9358f37e0046b010c334e87">More...</a><br /></td></tr>
<tr class="separator:a19f2a2270bc7aa8c4177d6e384197ea2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a84ed8d51d0d2793c3477cd51f373c3d0"><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="unionCPACR__Type.html#a68d69635225dd479d3035cc51b4c40ce">CP12</a>:2</td></tr>
<tr class="memdesc:a84ed8d51d0d2793c3477cd51f373c3d0"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit:24..25 Access rights for coprocessor 11  <a href="unionCPACR__Type.html#a68d69635225dd479d3035cc51b4c40ce">More...</a><br /></td></tr>
<tr class="separator:a84ed8d51d0d2793c3477cd51f373c3d0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6f87b61fd77f0a9b598e5decd9d539ce"><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="unionCPACR__Type.html#a45d9be266fc37a6ff9f31c2bef897f90">CP13</a>:2</td></tr>
<tr class="memdesc:a6f87b61fd77f0a9b598e5decd9d539ce"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit:26..27 Access rights for coprocessor 11  <a href="unionCPACR__Type.html#a45d9be266fc37a6ff9f31c2bef897f90">More...</a><br /></td></tr>
<tr class="separator:a6f87b61fd77f0a9b598e5decd9d539ce"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6908298e0b73b5f2b11e7f19cdbc2fab"><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="unionCPACR__Type.html#ac6f2f67dd0250b9dc9a8271a05655bbe">TRCDIS</a>:1</td></tr>
<tr class="memdesc:a6908298e0b73b5f2b11e7f19cdbc2fab"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 28 Disable CP14 access to trace registers  <a href="unionCPACR__Type.html#ac6f2f67dd0250b9dc9a8271a05655bbe">More...</a><br /></td></tr>
<tr class="separator:a6908298e0b73b5f2b11e7f19cdbc2fab"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aed42896bdcf2d2304b27e2e3e9f552c3"><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="unionCPACR__Type.html#a6206695a548b18ce0e2ea5276d1eef1d">D32DIS</a>:1</td></tr>
<tr class="memdesc:aed42896bdcf2d2304b27e2e3e9f552c3"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 30 Disable use of registers D16-D31 of the VFP register file  <a href="unionCPACR__Type.html#a6206695a548b18ce0e2ea5276d1eef1d">More...</a><br /></td></tr>
<tr class="separator:aed42896bdcf2d2304b27e2e3e9f552c3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:abe3c4303b5b2302adb3c05fd35ffd3a9"><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="unionCPACR__Type.html#a792fabd71db2311eefbc9b896db37986">ASEDIS</a>:1</td></tr>
<tr class="memdesc:abe3c4303b5b2302adb3c05fd35ffd3a9"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 31 Disable Advanced SIMD Functionality  <a href="unionCPACR__Type.html#a792fabd71db2311eefbc9b896db37986">More...</a><br /></td></tr>
<tr class="separator:abe3c4303b5b2302adb3c05fd35ffd3a9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac3126dff3427fa6f4ab48524d473aa12"><td class="memItemLeft" valign="top">}&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionCPACR__Type.html#ac3126dff3427fa6f4ab48524d473aa12">b</a></td></tr>
<tr class="memdesc:ac3126dff3427fa6f4ab48524d473aa12"><td class="mdescLeft">&#160;</td><td class="mdescRight">Structure used for bit access.  <br /></td></tr>
<tr class="separator:ac3126dff3427fa6f4ab48524d473aa12"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae2d9d724aff1f8f0060738f5d4527c33"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionCPACR__Type.html#ae2d9d724aff1f8f0060738f5d4527c33">w</a></td></tr>
<tr class="memdesc:ae2d9d724aff1f8f0060738f5d4527c33"><td class="mdescLeft">&#160;</td><td class="mdescRight">Type used for word access.  <br /></td></tr>
<tr class="separator:ae2d9d724aff1f8f0060738f5d4527c33"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table>
<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
<div class="textblock"><p>Bit field declaration for CPACR layout. </p>
</div><h2 class="groupheader">Field Documentation</h2>
<a id="a792fabd71db2311eefbc9b896db37986" name="a792fabd71db2311eefbc9b896db37986"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a792fabd71db2311eefbc9b896db37986">&#9670;&#160;</a></span>ASEDIS</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">uint32_t CPACR_Type::ASEDIS</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>bit: 31 Disable Advanced SIMD Functionality </p>

</div>
</div>
<a id="ac3126dff3427fa6f4ab48524d473aa12" name="ac3126dff3427fa6f4ab48524d473aa12"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ac3126dff3427fa6f4ab48524d473aa12">&#9670;&#160;</a></span></h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
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          <td class="memname">struct  { ... }  CPACR_Type::b</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Structure used for bit access. </p>

</div>
</div>
<a id="a1a29bc40d708ac1a43153b11f60b8195" name="a1a29bc40d708ac1a43153b11f60b8195"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a1a29bc40d708ac1a43153b11f60b8195">&#9670;&#160;</a></span>CP0</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">uint32_t CPACR_Type::CP0</td>
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      </table>
</div><div class="memdoc">

<p>bit: 0..1 Access rights for coprocessor 0 </p>

</div>
</div>
<a id="acb2055cdbdf2a6c9b8279dc6f7cbc624" name="acb2055cdbdf2a6c9b8279dc6f7cbc624"></a>
<h2 class="memtitle"><span class="permalink"><a href="#acb2055cdbdf2a6c9b8279dc6f7cbc624">&#9670;&#160;</a></span>CP1</h2>

<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">uint32_t CPACR_Type::CP1</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>bit: 2..3 Access rights for coprocessor 1 </p>

</div>
</div>
<a id="a0275dc6b0eb9f906ebc5c6431b03dc4e" name="a0275dc6b0eb9f906ebc5c6431b03dc4e"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a0275dc6b0eb9f906ebc5c6431b03dc4e">&#9670;&#160;</a></span>CP10</h2>

<div class="memitem">
<div class="memproto">
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          <td class="memname">uint32_t CPACR_Type::CP10</td>
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<p>bit:20..21 Access rights for coprocessor 10 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ac54b8897f9358f37e0046b010c334e87">&#9670;&#160;</a></span>CP11</h2>

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<p>bit:22..23 Access rights for coprocessor 11 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a68d69635225dd479d3035cc51b4c40ce">&#9670;&#160;</a></span>CP12</h2>

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<p>bit:24..25 Access rights for coprocessor 11 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a45d9be266fc37a6ff9f31c2bef897f90">&#9670;&#160;</a></span>CP13</h2>

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<p>bit:26..27 Access rights for coprocessor 11 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a2553fcdfd94ffc09407db9da9db9d586">&#9670;&#160;</a></span>CP2</h2>

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<p>bit: 4..5 Access rights for coprocessor 2 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#af245b8dabfea0bf7dc06f5d4de7bfa79">&#9670;&#160;</a></span>CP3</h2>

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<p>bit: 6..7 Access rights for coprocessor 3 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a6424b7a81a440217aab8e51e4b623adb">&#9670;&#160;</a></span>CP4</h2>

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<p>bit: 8..9 Access rights for coprocessor 4 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ad5c0b15cd6a01a6f1db398e020809573">&#9670;&#160;</a></span>CP5</h2>

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<p>bit:10..11 Access rights for coprocessor 5 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ad898cab7c89a07b80068d141ced869e3">&#9670;&#160;</a></span>CP6</h2>

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<p>bit:12..13 Access rights for coprocessor 6 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a12002991719fb1af7a5db9a73deb323d">&#9670;&#160;</a></span>CP7</h2>

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<p>bit:14..15 Access rights for coprocessor 7 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a5a6f694264518a813bdbc202ff47664f">&#9670;&#160;</a></span>CP8</h2>

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<p>bit:16..17 Access rights for coprocessor 8 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a4de69636eb450fcc3f5f3e4a19a869f5">&#9670;&#160;</a></span>CP9</h2>

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<p>bit:18..19 Access rights for coprocessor 9 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a6206695a548b18ce0e2ea5276d1eef1d">&#9670;&#160;</a></span>D32DIS</h2>

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<p>bit: 30 Disable use of registers D16-D31 of the VFP register file </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ac6f2f67dd0250b9dc9a8271a05655bbe">&#9670;&#160;</a></span>TRCDIS</h2>

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<p>bit: 28 Disable CP14 access to trace registers </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ae2d9d724aff1f8f0060738f5d4527c33">&#9670;&#160;</a></span>w</h2>

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<p>Type used for word access. </p>

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